Characterization and Modeling of Through Silicon Via (TSV) and its Impact on 3D Circuits and Systems (Karakterisering en modellering van Through Silicon Via (TSV) en de impact ervan op 3D circuits en systemen)

Performance of deep-sub micrometer Very Large Scale Integrated (VLSI) circuits is being increasingly dominated by global interconnects due to decreasing wire pitch and increasing die size. Additionally, smaller foot print and heterogeneous integration of different technologies in one single system on chip (SoC) is becoming highly desirable for modern applications such as biomedical and multimedia systems. Planar (2D) IC technology may not be suitable or economically viable for this purpose and 3D ICs promise to be a viable technology to meet Moore s law in the coming decade. Amongst many variants in 3D technology, 3D Stacked Integrated Circuits (SIC) with Through Silicon Vias (TSV) possess the potential to build high density 3D interconnects. TSVs act as an interconnection between the vertical dies and are different from 2D interconnects as the vertical interconnects pass through silicon rather than dielectric medium embedding 2D interconnects. This thesis is aimed at the characterization and modeling the behavior of TSVs and deciphering their impact on 3D circuits and systems. The parasitic resistance (R), inductance (L) and capacitance (C) of TSVs are analyzed from the fundamental electro dynamic principles and the models are verified with the numerical simulations as well as experimental results. A lumped RC model of the TSV for circuit simulations is framed and employed for 3D circuit simulations matching the model behavior with on-chip characterization results. The validated analytical model of the TSV not only provides accurate RLC estimations for the designers to create high performance 3D circuits and systems but has also been used to guide technologists towards optimal TSV architectures. Power-delay characteristics of 2D/3D Ring Oscillators (RO) along with an intuitive Elmore analysis of a simple 3D circuit are used to demonstrate that the TSV capacitance has the most predominant impact on 3D circuits and systems. The merits and demerits of the existing ideas to reduce the TSV capacitance are analyzed and a method to reduce the TSV capacitance by operating the TSV in depletion by tailoring the oxide charges is proposed. The reproducibility of the proposed method is tested in two different processing lines and the critical process improvements are highlighted. A high temperature TSV model matching the high temperature TSV characterization results is proposed in addition to analyzing the impact of various technology parameters on the rise of the TSV capacitance due to temperature. System level modeling of 3D IC is performed to derive the total wiring net length (in gate pitches) for a given TSV technology. Total wiring net length provides an elementary criterion to select a particular 2D or 3D technology for the design implementation in the initial design phase. Comparison of total wiring net length of a 2D IC and 3D IC for a given TSV technology is performed and it is highlighted that the 3D ICs become a viable option for higher gate count designs. The optimal number of tiers providing reduced wiring net lengthfor a given gate count is identified. The impact of various TSV generations on the wiring net length estimations is analyzed as well. It is observed that for a wide range of gate counts and number of 3D tiers, the capacitance of the TSV may prove to be a crucial bottleneck for the 3D design implementation. The impact of 3D design on VLSI scaling is also analyzed and it is estimated that the 3D design implementation in the precedent technology nodes can offer better performance compared to the state of the art 2D implementation. Thus, 3D technology can certainly be leveraged to prolong scaling of VLSI systems.Contents Acknowledgements i Abstract v Samenvatting vii List of Symbols xv List of Acronym xix List of Figures xxi List of Tables xxix 1. Introduction 1 1.1. Three Dimensional ICs – An Introduction 2 1.2. Three Dimensional ICs – A Technology perspective 6 1.2.1. Wire-bonding 7 1.2.2. Micro-bumps 7 1.2.3. Contactless technologies 8 1.2.3.1. Capacitive Coupling 9 1.2.3.2. Inductive Coupling 10 1.2.4. Monolithic 3D Integration 11 1.2.5. 3D Integration with Interposers 12 1.2.6. Through Silicon Via (TSV) based 3D Integration 13 1.3. Thesis Scope 20 1.4. Manuscript Organization 23 Bibliography 25 2. Electrical Characterization & Modeling of Through Silicon Via (TSV) for 3D ICs 31 2.1. Introduction 32 2.2. RTSV, LTSV & CTSV Modeling 33 2.2.1. RTSV Model 34 2.2.2. LTSV Model 36 2.2.3. CTSV Model 37 2.3. TSV Electrical Characterization Results 42 2.3.1. Front End CMOS Devices 42 2.3.2. RTSV Characterization 45 2.3.3. LTSV Characterization 48 2.3.4. CTSV Characterization 48 2.3.5. TSV Leakage Current Characterization 52 2.3.6. TSV Crosstalk 54 2.3.7. 2D/3D Ring Oscillators 57 2.4. TSV Architectures & RLC Prognostics 61 2.5. Impact of TSV on 3D circuits 66 2.6. Conclusions 70 Bibliography 71 3. TSV Capacitance Reduction Techniques 75 3.1. Introduction 76 3.2. Prior Art 78 3.3. Proposed Method 79 3.4. Reproducibility of the Proposed Method 86 3.6. Conclusions 93 Bibliography 95 4. Temperature Dependent TSV Electrical Characterization and Modeling 99 4.1. Introduction 100 4.2. High Temperature TSV Characterization 101 4.2.1. RTSV at high temperature 101 4.2.2. TSV leakage at high temperature 102 4.2.3. CTSV at high temperature 103 4.2.3.1. Temperature dependent TSV capacitance model 106 4.2.3.2. Exploration of Technology Parameters 110 4.2.4. 2D/3D RO performance at high temperature 112 4.3. Conclusions 113 Bibliography 115 5. 2D Versus 3D Design Space Exploration 119 5.1. Introduction 120 5.2. Wire Length estimation of 2D ICs 122 5.3. Wire Length estimation of 3D ICs 127 5.4. Results and Discussions 140 5.5. Conclusion 148 Bibliography 150 6. Conclusions & Future Work 153 6.1. Conclusions 154 6.2. Future work 158 Bibliography 160 Appendix-I 163 Appendix-II 169 List of Publications & Awards 177nrpages: 216status: publishe

Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure

Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without TSVs. The stability of this structure was investigated by thermal cycling tests. Measurements after 1000 cycles between -55 and 125°C demonstrated good robustness of the stacked integrated circuit (SIC) structure. Residual stress induced by the TSVs was experimentally examined by micro-Raman spectroscopy. The results revealed that TSV induced stress is negligible for carrier mobility in this technology.status: publishe